In the fabrication of a semiconductor integrated circuit (IC), material is deposited, or otherwise formed, in layers. Some of these layers are then patterned to form the individual devices within the IC. Layers of conductive material (e.g., metal, such as aluminum) formed over the individual devices are patterned to form metal lines. The metal lines provide connections with respect to the individual devices of the IC.
Generally, a conductive layer to be patterned is supported by a substrate during processing. During patterning, a photoresist layer is formed over the conductive layer to be patterned. The photoresist layer is then exposed to ultraviolet radiation as part of a photolithographic process used to perform the patterning. The photoresist layer is exposed such that a desired pattern is imparted to the photoresist layer after its selective removal. The photoresist is patterned to define features having critical dimensions in underlying layers. To remove portions of the photoresist layer (exposed or unexposed, depending on the type of photoresist used), a developer solution is used. The underlying conductive layer to be patterned is, thus, exposed in regions where the photoresist was removed using the developer solution. An etchant is then typically used to remove the underlying conductive layer, resulting in a patterned conductive layer supported by the substrate.
At the interconnect level in the fabrication process, a significantly rough surface topography typically exists due to the numerous patterned layers thereunder. This rough surface topography causes an uneven level of reflection from the conductive layer into the overlying photoresist layer when the photoresist is exposed to ultraviolet radiation. The uneven level of reflection results in poor definition of the pattern in the photoresist layer. Thus, conventionally, to control the amount of reflection from underlying layers, titanium nitride (TiN) is conventionally formed between the underlying layer and the photoresist layer to act as an antireflective layer.
As device density is increasing to meet consumer demands for faster processing of data, the amount of interconnect required between devices is also increasing. To accommodate this increase in the amount of interconnects needed per chip, the pitch (i.e., width) of metal lines and spaces therebetween is being decreased and the interconnects are being formed in an increasing number of layers within the IC. As the pitch tightens, such as, for example, about 0.6 microns and below, adhesion of photoresist to the underlying TiN layer is problematic. As a result of poor photoresist adhesion to the TiN layer, patterning of the underlying conductive layer is also poor, particularly at the interface between the photoresist and the underlying layer. Therefore, there is a need for methods to improve resist adhesion on a TiN layer for use in patterning of underlying conductive layers.